Renesas Electronics /R7FA6M3AH /GPT32EH0 /GTBER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as GTBER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)BD0 (00)CCRA 0 (00)CCRB 0 (00)PR0 (0)CCRSWT 0 (00)ADTTA 0 (0)ADTDA 0 (00)ADTTB 0 (0)ADTDB

PR=00, ADTDB=0, BD=0, ADTDA=0, CCRA=00, ADTTB=00, CCRB=00, ADTTA=00, CCRSWT=0

Description

General PWM Timer Buffer Enable Register

Fields

BD

BD[3]: GTDV Buffer Operation DisableBD[2]: GTADTR Buffer Operation DisableBD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable

0 (0): Enable buffer operation

1 (1): Disable buffer operation

CCRA

GTCCRA Buffer Operation

0 (00): Buffer operation is not performed

1 (01): Single buffer operation (GTCCRA <–> GTCCRC)

2 (10): Double buffer operation (GTCCRA <–> GTCCRC <–> GTCCRD)

3 (11): Double buffer operation (GTCCRA <–> GTCCRC <–> GTCCRD)

CCRB

GTCCRB Buffer Operation

0 (00): Buffer operation is not performed

1 (01): Single buffer operation (GTCCRB <–> GTCCRE)

2 (10): Double buffer operation (GTCCRB <–> GTCCRE <–> GTCCRF)

3 (11): Double buffer operation (GTCCRB <–> GTCCRE <–> GTCCRF)

PR

GTPR Buffer Operation

0 (00): Buffer operation is not performed

1 (01): Single buffer operation (GTPBR --> GTPR)

2 (10): Double buffer operation (GTPDBR --> GTPBR --> GTPR)

3 (11): Double buffer operation (GTPDBR --> GTPBR --> GTPR)

CCRSWT

GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0.

0 (0): no effect

1 (1): Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1.

ADTTA

GTADTRA Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.

0 (00): No transfer

1 (01): Transfer at crest

2 (10): Transfer at trough

3 (11): Transfer at both crest and trough

ADTDA

GTADTRA Double Buffer Operation

0 (0): Single buffer operation (GTADTBRA --> GTADTRA)

1 (1): Double buffer operation (GTADTDBRA --> GTADTBRA --> GTADTDRA)

ADTTB

GTADTRB Buffer Transfer Timing Select in the Triangle wavesNOTE: In the Saw waves, values other than 0 0: Transfer at an underflow (in down-counting) or overflow (in up-counting) is performed.

0 (00): No transfer

1 (01): Transfer at crest

2 (10): Transfer at trough

3 (11): Transfer at both crest and trough

ADTDB

GTADTRB Double Buffer Operation

0 (0): Single buffer operation (GTADTBRB --> GTADTRB)

1 (1): Double buffer operation (GTADTDBRB --> GTADTBRB --> GTADTDRB)

Links

()